The invention relates to a circuit for generating an inverse signal of a digital signal with a minimal delay difference between the inverse signal and the digital signal.
Such a circuit is known from German patent document 43 15 298. The circuit described therein requires an inverter with an additional clock circuit whose frequency must be related to the frequency of the signal to be inverted. The clock signal determines the tempo in which and the moments at which the edges of the digital signal and the inverted signal are synchronized by means of the circuit disclosed. A digital signal having edges at moments not related to the edges of the clock signal cannot be inverted with the circuit under discussion in such a manner that the edges, and possibly the steepnesses thereof, of the digital signal and the inverted signal are representative of the original signal.
Timing may be highly critical in circuits on occasions in the sense that a signal must be available in the normal as well as the inverse form simultaneously, such that no delay obtains between the edges of the two signals. That is to say, the edges of the two signals must exactly coincide in time.
If there are two signal paths, the digital signal having to follow the one signal path and the inverted digital signal having to follow the other signal path, the simplest manner of generating said signals is to include one more inverter in one of the two paths. It is known that this results in unequal delays, i.e. an additional gate delay of the inverter, so that the edges of the digital signal and the inverse signal no longer coincide.
It is also known to include a so-called pass gate in the signal path in which the signal is present for the shortest period as compared with the other signal path, with the purpose of compensating to a certain extent the difference in delay caused by the additional inverter. A difference does remain, however, because the manners in which the delays are created are dissimilar. The idle time which arises in an inverter as a result of charging/discharging of the input across a threshold voltage is not present in the pass gate.
It is an object of the invention to provide a circuit in which the disadvantages detailed above have been largely or wholly eliminated.
According to the invention, such a circuit is for this purpose characterized in that a first and a second inverter circuit are connected in series, in that an input of the first inverter circuit forms the input of the circuit, in that an output of the second inverter circuit forms a first output of the circuit for supplying the digital signal, in that the input of the first inverter circuit is connected to an adjustment input of a pass-through circuit with threshold action, in that a junction point, at which an output of the first inverter circuit is connected to an input of the second inverter circuit, is connected to a control input of the pass-through circuit with threshold action, which pass-through circuit with threshold action supplies a signal at an output thereof equal to the signal at the junction point and having a delay which is substantially equal to the delay introduced by the second inverter circuit, said output of the pass-through circuit with threshold action forming a second output of the circuit for supplying the inverse signal.
It is achieved thereby that the edges of the digital signal and of the inverse signal are made to coincide substantially by means of a simple circuit. It is also achieved that the operation of the circuit is independent of an additional clock signal as described in German patent document 43 15 298.
A preferred embodiment of a circuit according to the invention is characterized in that the first and the second inverter are built up from MOS-FETs, and in that the pass-through circuit with threshold action comprises an N-type and a P-type MOS-FET whose gates are interconnected and form the adjustment input of the pass-through circuit with threshold action, whose sources are interconnected and form the control input of the pass-through circuit with threshold action, and whose drains are interconnected and form the output of the pass-through circuit with threshold action.
The operation with MOS-FETs achieves that a very accurate circuit can be designed and manufactured in a simple manner, in which the various delays in the individual circuit components can be determined beforehand and can be satisfactorily maintained during production.